RISC-V RV32I RTL Design using Verilog HDL
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL.
As part of this training you will be trained extensively on Verilog HDL RTL, how you can use the language features for RTL synthesis and simulation, using various lab exercises. Finally, you will implement the RTL design of a pipeline RISC-V processor in Verilog HDL, following best design and verification practices, and coding styles.
1: RISC-V Instruction Set Architecture
2: RISC-V RV32I Reference Guide
very well explained.