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RISC-V RV32I RTL Design using Verilog HDL

4.7
(158 ratings)
Course Instructor Sivakumar P R
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Course Overview

Course Curriculum

1 Subject

RISC-V RV32I RTL Design using Verilog HDL

12 Exercises 52 Learning Materials

RISC-V Instruction Set Architecture

Why RISC-V Processor?

Video
6:50

RISC-V processor overview

Video
10:24

RISC-V ISA Overview

Video
12:13

RV32I R Type Instruction

Video
9:29

RV32I I Type Instruction

Video
7:47

RV32I S and B Type Instructions

Video
11:55

RV32I J and U Type Instructions

Video
12:35

RV32I Assembly Programs and Summary

Video
19:22

Knowledge Check - RISC-V Instruction Set Architecture

Exercise

RISC-V RV32I Reference Guide

RISC-V RV32I Quick Reference Guide

PDF

RISC-V RV32I RTL Architecture Design

RISC-V Execution Stages and Flow

Video
8:36

RISC-V Register File and RV32I Instructions Format

Video
12:52

RV32I R Type ALU Datapath

Video
9:29

RV32I I Type ALU Datapath

Video
6:33

RV32I S Type ALU Datapath - Load & Store

Video
13:4

RV32I B Type ALU Datapath

Video
8:23

RV32I J Type ALU Datapath JAL & JALR

Video
9:26

RV32I U Type ALU Datapath and Summary

Video
10:18

Knowledge Check : RISC-V RTL Design

Exercise

RISC-V RV32I 5 Stage Pipelined RTL Design

CPU Performance and RISC-V 5 Stage Pipeline Overview

Video
15:12

RISC-V 5 Stage Pipeline Data Hazards & Design Approach

Video
16:3

RISC-V 5 Stage Pipeline Control Hazards & Design Approach

Video
13:51

Knowledge Check : RISC-V Pipelined RTL Design

Exercise

Verilog HDL

Setting Expectations - Course Agenda

Video
12:4

Introduction to Verilog HDL

Video
23:59

Knowledge Check - Introduction to Verilog HDL

Exercise

Verilog HDL Reference Guide

Verilog HDL - Quick Reference Guide

PDF

Verilog HDL: Data Types

Data Types

Video
30:4

Knowledge Check - Data Types

Exercise

Verilog HDL: Operators

Verilog Operators

Video
30:6

Knowledge Check - Verilog Operators

Exercise

Advanced Verilog for Verification

Advance Verilog for Verification

Video
29:7

Knowledge Check - Verilog for Verification

Exercise

Verilog HDL: Assignments

Assignments

Video
23:21

Knowledge Check - Assignments

Exercise

Verilog HDL: Structured Procedures

Structured Procedures

Video
20:31

Knowledge Check - Structured Procedures

Exercise

Verilog HDL : Synthesis Coding Style

Synthesis Coding Style

Video
20:59

Knowledge Check - Synthesis Coding Style

Exercise

Verilog HDL: Finite State Machine

Finite State Machine

Video
16:19

Knowledge Check - Finite State Machine

Exercise

Summary - Verilog HDL

Summary

Video
23:58

Verilog HDL : Labs

Instructions - Verilog Labs

PDF

Verilog Lab Manual

PDF

EDA Tools - Installation Guide

Video
18:50

EDA Tools - User Guide

Video
5:22

Solution to Lab 1

Video
23:43

Solution to Lab 2

Video
10:28

Solution to Lab 3

Video
6:1

Solution to Lab 4

Video
6:53

Solution to Lab 5

Video
6:41

Solution to Lab 6

Video
8:18

Project: RISC-V RV32I Multi stage pipeline processor RTL Design

The RISC-V Instruction Set Manual

PDF

MSRV32I Core Design Specification

PDF

RISC-V RV32I - Quick Reference Guide for Instrcutions

PDF

Final Test: RISCV design

RISCV design

Exercise

RISC-V RTL Design

ALU Design

Video
11:3

ALU Verification

Video
7:48

Integer file design

Video
7:12

Integer File Verification

Video
9:19

RISC-V RTL Design & Verification Part -1

Video
13:41

RISC-V RTL Design & Verification Part -2

Video
12:22

RISC-V RTL Design & Verification Part -3

Video
19:45

RISC-V RTL Design & Verification Part -4

Video
6:21

Course Instructor

tutor image

Sivakumar P R

17 Courses   •   1935 Students

CEO and Founder, Maven Silicon

Ratings & Reviews

4.7 /5

166 ratings

158 reviews

5

69%

4

31%

3

0%

2

0%

1

0%
SS
Sameer Singh

3 months ago

RR
RITHAMI R

9 months ago

its a goood course
GH
GOLLAPUDI HEMANTH

9 months ago

LEARNED A LOT

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