RISC-V RV32I RTL Design using Verilog HDL

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RISC-V RV32I RTL Design using Verilog HDL

This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL.

As part of this training you will be trained extensively on Verilog HDL RTL, how you can use the language features for RTL synthesis and simulation, using various lab exercises. Finally, you will implement the RTL design of a pipeline RISC-V processor in Verilog HDL, following best design and verification practices, and coding styles.

Modules:

RISC-V Instruction Set Architecture
RISC-V RV32I 5 stage pipeline processor RTL Design
Verilog HDL Theory and Labs
Project: RISC-V RV32I 5 stage pipeline processor Design

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Curriculum

1: RISC-V Instruction Set Architecture
Lecture 1 Why RISC-V Processor? 06:50
Lecture 2 RISC-V processor overview 10:24
Lecture 3 RISC-V ISA Overview 12:12
Lecture 4 RV32I – R Type Instruction 09:28
Lecture 5 RV32I – I Type Instruction 07:47
Lecture 6 RV32I – S and B Type Instructions 11:54
Lecture 7 RV32I – J and U Type Instructions 12:35
Lecture 8 RV32I – Assembly Programs and Summary 19:22
Quiz 1 Knowledge Check - RISC-V Instruction Set Architecture 10 Questions

2: RISC-V RV32I Reference Guide
Lecture 9 RISC-V RV32I Quick Reference Guide 5 Pages

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