RISC-V RV32I RTL Verification using UVM

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RISC-V RV32I RTL Verification using UVM

This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM.

As part of this training you will be trained extensively on UVM, how you can use the language and UVM methodology features for the RTL verification, using various lab exercises and IP and SoC case studies.

Finally, you will implement a UVM class-based verification environment and verify the pipeline RISC-V processor RTL design implemented in Verilog HDL, following best verification practices and coding styles.

Modules:

RISC-V Instruction Set Architecture
RISC-V RV32I 5 stage pipeline processor
Universal Verification Methodology - Theory and Labs
Project: RISC-V RV32I 5 stage pipeline processor Verification

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Curriculum

1: RISC-V Instruction Set Architecture
Lecture 1 Why RISC-V Processor? 06:50
Lecture 2 RISC-V processor overview 10:24
Lecture 3 RISC-V ISA Overview 12:12
Lecture 4 RV32I – R Type Instruction 09:28
Lecture 5 RV32I – I Type Instruction 07:47
Lecture 6 RV32I – S and B Type Instructions 11:54
Lecture 7 RV32I – J and U Type Instructions 12:35
Lecture 8 RV32I – Assembly Programs and Summary 19:22
Quiz 1 Knowledge Check - RISC-V Instruction Set Architecture 10 Questions

2: RISC-V RV32I Reference Guide
Lecture 9 RISC-V RV32I Quick Reference Guide 0 Pages

VIew Full Curriculum

Shashank Mistry
28 April 2022

good
Ronak Vithlani
8 March 2022

Nice course, quick overview to uvm and good beginning for RISC V verification.
Rashmi Hrishikesh Waghmare
21 February 2022

Very useful course
Ravi Patel
30 September 2021

Overall Good content of course.
Sri Srujan
14 July 2021

If you're familiar with System Verilog, then this course is the right addition to upgrade your skill.