RISC-V RV32I RTL Verification using UVM
This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM.
As part of this training you will be trained extensively on UVM, how you can use the language and UVM methodology features for the RTL verification, using various lab exercises and IP and SoC case studies.
Finally, you will implement a UVM class-based verification environment and verify the pipeline RISC-V processor RTL design implemented in Verilog HDL, following best verification practices and coding styles.
1: RISC-V Instruction Set Architecture
2: RISC-V RV32I Reference Guide