This SystemVerilog [SV] hands-on module provides all the lab exercises and case study examples to understand all the SystemVerilog language concepts, syntax and semantics of all the language features very well. With this lab practice and coding expertise, one can understand how a SV class based verification environment can be created to verify the RTL design.
If you want to learn SystemVerilog theory concepts then you can subscribe to any of the following courses also along with this course.Read full details
1: SV Lab Setup guide - Reference manuals
2: Linux Operating System
3: SystemVerilog Labs
Concept are explained deeply.Got good knowledge of system verilog.
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