This SystemVerilog hands-on course explains all the language data types and concepts, especially how we can use all the language features to create a class-based verification environment. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, etc. in detail and trains you extensively to create the class-based verification environment and guide you to do the lab exercises to understand all the concepts very well.
Any electronics/electrical engineering graduate with a good knowledge or experience in RTL design using Verilog HDL.Read full details
1: SystemVerilog Language Concepts
2: SystemVerilog - Quick Reference Guide
Very nice and teaching also good thanks Sivakumar
Easy to understand
Its a great course !
Its really very nice course thanks Sivakumar, everthing explained one by one.
Very good for the beginners
Good explanation on System verilog fundamentals
Was very informative and detailed. Good explanations.
Course was helpful in understanding SV concepts
Very good course for beginners.
So nicely explained.
Good. Thank you
Excellent Explanation of the whole Verification Enviroment and its components
Best explanation for the different TB components and their workings in the Verification Enviroment
Interesting and informative
I was able to obtain knowledge on system verilog
This is an excellent course. The instructor is very thorough. Excellent!