This Systemverilog course explains all the language data types and concepts, especially how we can use all the language features to create a class-based verification environment. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, etc. in detail and trains you extensively on creating the class-based verification environment.
Any electronics/electrical engineering graduate with a good knowledge or experience in RTL design using Verilog HDL.Read full details
1: SystemVerilog Language Concepts
2: SystemVerilog Datatypes
This is an excellent course. The instructor is very thorough. Excellent!