Universal Verification Methodology
Discover Universal Verification Methodology with Maven Silicon. Learn the industry-standard techniques for systematic and efficient VLSI verification.
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Course Overview
Welcome to the Universal Verification Methodology course – your comprehensive guide to mastering UVM for robust hardware verification. From an overview of UVM to in-depth modules covering UVM TB architecture, factory, stimulus modeling, and much more, this course is designed to equip you with the skills needed for effective verification methodologies. Engage in UVM Labs, create testbench components, and explore the Register Abstraction Layer. Join us on this enlightening journey into the world of Universal Verification Methodology!
Course Curriculum
1 Subject
Universal Verification Methodology
12 Exercises • 45 Learning Materials
Universal Verification Methodology Overview
UVM_Introduction
Advanced_UVM_CaseStudies
Knowledge Check : Introduction to UVM
UVM - Quick Reference Guide
UVM - Quick Reference Guide
UVM TB Architecture and Base Class Hierarchy
UVM Testbench Architecture
UVM Base Class Hierarchy
Knowledge Check - UVM TB Architecture and Base Class Hierarchy
UVM Factory
UVM Factory - Importance of using factory
UVM Factory - Registration Process
UVM Factory - Create Method and Factory Overriding
Knowledge Check - UVM Factory
UVM - Stimulus Modelling & Testbench Overview
UVM Stimulus Modelling - Predefined Methods and Field Registration Process
UVM Stimulus Modelling - Overriding the predefined do_ methods
UVM - TB Overview
Knowledge Check - UVM Stimulus Modelling & TB Overview
UVM Phases & Reporting Mechanism
UVM Phases - Necessity of Phases & pre-run Phases
UVM Phases - Run Phase, post-run Phases and Objection Mechanism
UVM Reporting Mechanism
Knowledge Check - UVM Phases & Reporting Mechanism
UVM TLM Ports and Configuration
UVM TLM Ports - Blocking put and get ports
UVM TLM Ports - TLM FIFO and Analysis Ports
UVM Configuration - Introduction to Configuration Facility
UVM Configuration - Configuration class and Configuration of Virtual Interface
Knowledge Check - UVM TLM Ports and Configuration
UVM - Creating UVM Testbench Components
Creating UVM TB Components - Sequencers & Drivers
Creating UVM TB Components - Monitor, Agents, Env and Testcases
Knowledge Check - UVM - Creating UVM Testbench Components
UVM Sequences
UVM Sequences - Introduction and Sequence item flow
UVM Sequences - Starting the sequences and Default Sequence
Knowledge Check - UVM Sequences
UVM - Virtual Sequences & Virtual Sequencers
UVM Virtual Sequences & Virtual Sequencers - Introduction
UVM Virtual Sequences & Virtual Sequencers - implementation
Knowledge Check - UVM - Virtual Sequences & Virtual Sequencers
UVM Callbacks & Events
UVM Callbacks
UVM Events
Knowledge Check - UVM Callbacks & Events
UVM - Creating Scoreboard
UVM Creating Scoreboard
Knowledge Check - UVM - Creating Scoreboard
UVM Lab Setup guide - reference manuals
UVM Labs User Guide
VPN Configuration Guide
UVM Labs
Lab1 Solution : Stimulus Modeling
Lab2 Solution : Factory Overriding
Lab3 Solution : UVM Phases
Lab4 Solution : Creating UVM agent
Lab5 Solution : UVM Sequences
Lab6 Solution : Virtual Interface
Lab7 Solution : Agent Integration
Lab8 Solution : UVM Socreboard
Lab9 Solution : SoC - UVM VE implementation
Lab10 Solution : Coverage & Regression
UVM Lab Manual
Feedback Form
Feedback Form
UVM - Register Abstraction Layer
UVM RAL - Intro & Definition of Register Block
UVM RAL - Adapter, Predictor and Integration
UVM RAL - Definition of Register Sequences
Knowledge Check - UVM RAL
UVM - CaseStudies
Advanced_UVM_CaseStudies
Course Instructor
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Maven Silicon
251 Courses • 301818 Students
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