This UVM hands-on course begins with a good overview of UVM methodology, explaining the concepts like agents and UVCs with various examples like AHB UVCs and SOC UVM testbenches. With this overview it walks you through all the concepts like UVM TB frame work, base class library, factory, sequences, phases, reporting mechanism, TLM ports, virtual sequences, events, call backs, UVCs, Scoreboard, UVM environment, etc and guide you to do the lab exercises to understand all the concepts very well.
This course explains the need and usage of UVM with various examples like IP and SOC level testbenches. With the help of this hands-on course you can learn the nuts and bolts of UVM and grow as a UVM expert in the functional verification domain.
Prerequisite: Any electronics/electrical engineering graduate with a good knowledge or experience in RTL design and verification using SystemVerilog testbenches.Read full details
1: Universal Verification Methodology Overview
2: UVM TB Architecture and Base Class Hierarchy
3: UVM Factory