Agenda :

Overview of VLSI Design

RTL Design using Verilog HDL

Overview of Verilog
- Verilog Language Concepts
- Verilog Language Basics and Constructs
- Verilog Abstraction Levels
Data Types
- Data type concepts
- Nets and Registers
- Non hardware equivalent variables
- Arrays
Verilog Operators
- Logical operators
- Bitwise and Reduction operators
- Concatenation and Conditional
- Relational and Arithmetic
- Shift and Equality operators
- Operators precedence
Verilog Labs - Familiarisation with Verilog Syntax, Instantiation and Testbench

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Prof Prabhavati Bahirgonde
14 October 2019

The session conducted by Mr. Sivakumar, CEO is containing rich technical stuff. The students got an overall idea of the subject. In the curriculum we have the subject VLSI DESIGN next semester. If possible convey such a webinar in the future also.
P S PERIASAMY
12 September 2019

Excellent delivery of lecture and easily understandable by the students.
Pushpinder Sharma
12 September 2019

Very knowledgeable webinar. Expect more webinars in future thank you very much regards Pushpinder Sharma BFECT Bathinda
Rajoli Padmaja
28 August 2019

It was very interesting session.It gav e us the key idea about verilog design.Hope , it will be very helpful in our further higher studies. we have very much impressed and they have expalined each concept in quiet understandable manner.And they have cleared all our queries with very patience.
Chitra Pravin
28 August 2019

The overall session was very good.Started with VLSI intro and ended up with verilog operators. Students can able to get all the syntax of verilog and it will be useful for the program writing. nice..
mohamed
10 April 2019

the course is very helpful for university students
Nayana Ram
25 January 2019

Excellent learning
Sameera
25 January 2019

Knowledgeable session

VLSI Design using Verilog HDL Webinar