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This Verification Methodology course starts with a good overview and explains the need of verification. Then it explains the functional verification process, testbench architecture and constraint random coverage driven verification methodology in detail. Finally, it walks you through all the verification methodologies like linting, code coverage, functional coverage, verification planning & management and Assertion Based verification and give you a good exposure how we verify RTL design thoroughly.
Course Agenda:
Prerequisite:
Any electronics/electrical engineering graduate with a good knowledge in Digital Electronics and VLSI Design flow. Knowledge in RTL design using HDL is an added advantage.
Read full details1: Verification Methodology
20 December 2019
High quality specialized information presented in excellent way
20 December 2019
So far I am enjoying the course because it presents important information in a high-level and easy to understand manner
