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This Verification Methodology course starts with a good overview and explains the need of verification. Then it explains the functional verification process, testbench architecture and constraint random coverage driven verification methodology in detail. Finally, it walks you through all the verification methodologies like linting, code coverage, functional coverage, verification planning & management and Assertion Based verification and give you a good exposure how we verify RTL design thoroughly.
Course Agenda:
Prerequisite:
Any electronics/electrical engineering graduate with a good knowledge in Digital Electronics and VLSI Design flow. Knowledge in RTL design using HDL is an added advantage.
Read full details1: Verification Methodology
11 November 2022
Great course to get a basic insight into expansion of Verilog Test bench concepts and their advancements
13 September 2022
quite practical
31 May 2022
The instructor has madethe concepts lighter without degrading the quality of the course
11 May 2022
It's a good course for those who are starters in the Verification domain.
23 September 2021
well structured animations for better understandings and the way of teaching by siva sir is very easy to catch.
2 June 2021
The explanation was pretty good.
29 April 2021
Good
5 April 2021
good course
28 March 2021
gained some knowledge about the verification methodology
5 February 2021
nice explanation
29 January 2021
Basic knowledge regarding Verification explained well
16 January 2021
Good overview on how verification is actually done
8 January 2021
Again ,sir is explaining the terms in laymen terms which is quite easy to digest, rather than bookish language. Great learning
30 November 2020
Great course
29 June 2020
Nice
10 May 2020
Excellent Teaching and easy understanding
20 December 2019
High quality specialized information presented in excellent way
20 December 2019
So far I am enjoying the course because it presents important information in a high-level and easy to understand manner
