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Verification Methodology Overview

  • 4.8 | 20 Ratings
  • 206 Students enrolled
  • Certified course
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About Course

  Language English

This Verification Methodology course starts with a good overview and explains the need of verification. Then it explains the functional verification process, testbench architecture and constraint random coverage driven verification methodology in detail. Finally, it walks you through all the verification methodologies like linting, code coverage, functional coverage, verification planning & management and Assertion Based verification and give you a good exposure how we verify RTL design thoroughly.

Course Agenda:

  • Why Verification?
  • Functional Verification
  • Verification process
  • Reusable Testbench
  • Testbench Architecture
  • Directed Vs Random
  • CRCDV
  • RTL – FV Methodologies

Prerequisite:

Any electronics/electrical engineering graduate with a good knowledge in Digital Electronics and VLSI Design flow. Knowledge in RTL design using HDL is an added advantage.

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Curriculum

  • 1: Verification Methodology

  • Lecture 1 Introduction to Verification Methodology 22:24
  • Lecture 2 Verification Process 21:46
  • Lecture 3 Reusable TB 07:24
  • Lecture 4 Verification Environment Architecture 19:01
  • Lecture 5 Constraint Random Coverage Driven Verification 25:36
  • Lecture 6 Verification Methodologies & Summary 27:11
  • Quiz 1 Knowledge Check 15 Questions

Reviews

4.8
20 Ratings
5 80% 4 20% 3 0% 2 0% 1 0%
  • Pendekanti Venkata Sai Tharun Kumar
    10 May 2020

    Excellent Teaching and easy understanding

  • Mohamad Hazwan Haron
    20 December 2019

    High quality specialized information presented in excellent way

  • Joel Mandebi Mbongue
    20 December 2019

    So far I am enjoying the course because it presents important information in a high-level and easy to understand manner