This Verification Methodology course starts with a good overview and explains the need of verification. Then it explains the functional verification process, testbench architecture and constraint random coverage driven verification methodology in detail. Finally, it walks you through all the verification methodologies like linting, code coverage, functional coverage, verification planning & management and Assertion Based verification and give you a good exposure how we verify RTL design thoroughly.
Any electronics/electrical engineering graduate with a good knowledge in Digital Electronics and VLSI Design flow. Knowledge in RTL design using HDL is an added advantage.Read full details
1: Verification Methodology
Great course to get a basic insight into expansion of Verilog Test bench concepts and their advancements
The instructor has madethe concepts lighter without degrading the quality of the course
It's a good course for those who are starters in the Verification domain.
well structured animations for better understandings and the way of teaching by siva sir is very easy to catch.
The explanation was pretty good.
gained some knowledge about the verification methodology
Basic knowledge regarding Verification explained well
Good overview on how verification is actually done
Again ,sir is explaining the terms in laymen terms which is quite easy to digest, rather than bookish language. Great learning
Excellent Teaching and easy understanding
High quality specialized information presented in excellent way
So far I am enjoying the course because it presents important information in a high-level and easy to understand manner