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Verilog HDL

  • 4.9 | 8 Ratings
  • 18 Students enrolled
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About Course

  Language English

This Verilog course covers the coding for synthesis and simulation. It explains the concept of hardware description language and basic concepts like data types and operators. Then it explains advanced concepts like assignments, procedural blocks, synthesis coding style and testbench coding. This course is composed of theory modules, quiz, labs and project. You can watch the videos repeatedly to understand the theory well and practice more through quiz and labs. Doing the labs and projects will make you a hands-on RTL programmer.

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Curriculum

  • 1: Introduction to verilog HDL

  • Lecture 1 Setting Expectations - Course Agenda 12:00
  • Lecture 2 Introduction to Verilog HDL 23:59
  • Quiz 1 Knowledge Check - Introduction to Verilog HDL 5 Questions

  • 2: Data Types

  • Lecture 3 Data Types 30:04
  • Quiz 2 Knowledge Check - Data Types 10 Questions

  • 3: Verilog Operators

  • Lecture 4 Verilog Operators 30:06
  • Quiz 3 Knowledge Check - Verilog Operators 10 Questions

  • 4: Advanced Verilog for Verification

  • Lecture 5 Advance Verilog for Verification 29:06
  • Quiz 4 Knowledge Check - Advanced Verilog for Verification 10 Questions

  • 5: Assignments

  • Lecture 6 Assignments 23:20
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Reviews

4.9
8 Ratings
5 88% 4 13% 3 0% 2 0% 1 0%