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VLSI SoC Design Course

VLSI Verification - Corporate

  • 4.9 | 22 Ratings
  • 47 Students enrolled

About Course

  Language English

VLSI Verification Corporate course is for the working professionals who want to upskill on the latest ASIC verification methodologies, SystemVerilog and UVM and work directly on the customer projects as a verification expert.

This VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail.

SystemVerilog for Verification module trains you extensively on creating the testbenches using OOP, constraint random simulation and verification sign-off using functional coverage. Finally, it also walks you through UVM methodology concepts and explains the need of using IEEE standard methodologies like UVM to create SystemVerilog based testbenches.

USP: This verification course is very different from the standard textbooks and training courses available in the market. It is completely based on a standard testbench architecture which can be used for creating SystemVerilog testbenches and at the same they can be easily migrated to UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.

Any electronics engineer with good knowledge in RTL design using Verilog HDL can learn all the verification methodologies and SystemVerilog language concepts from this course and grow as a hand-on verification expert. 

Modules:

•       Verification Methodology Overview

•       Systemverilog for Verification

•       Universal Verification Methodology Overview


T&C: This free demo course does not include SystemVerilog Case Studies & Labs and UVM Theory & Labs. Please contact us to know about the price and bulk coupon discount options.

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Curriculum

  • 1: Verification Methodology Overview

  • Lecture 1 Introduction to Verification Methodology 22:24
  • Lecture 2 Verification Process 21:46
  • Lecture 3 Reusable TB 07:24
  • Lecture 4 Verification Environment Architecture 19:01
  • Lecture 5 Constraint Random Coverage Driven Verification 25:36
  • Lecture 6 Verification Methodologies & Summary 27:11
  • Quiz 1 Knowledge Check - Verification Methodology Overview 15 Questions
  • 2: SystemVerilog Language Concepts

  • Lecture 7 SV Concepts Agenda 06:37
  • Lecture 8 SV Overview 11:15
  • Lecture 9 SV Transactions 14:46
VIew Full Curriculum

Reviews

4.9
22 Ratings
5 91% 4 9% 3 0% 2 0% 1 0%
  • Vivek Tiwari from Microchip
    20 May 2020

    The material is helping in solving many of the small doubts we have related to SV and UVM

  • Sai Pavan from Signoff Semiconductors
    20 May 2020

    Explanation by the Siva Kumar sir was really good and brief

  • Ravi Shankar M from Caliber Interconnect Solutions
    20 May 2020

    Content was very clear and explained neatly with relevant examples

  • Sai Charan from Alpha Numero
    20 May 2020

    Detailed explanation

  • Nikhil P from VVDN Technologies
    20 May 2020

    System Verilog Concepts were explained beautifully

  • Aman Chaurasiya from Spicaworks
    20 May 2020

    All the concepts shared with example. The course is good for building verification understanding, mainly for SV

  • Muruganantham M from Mirafra
    10 May 2020

    Wide area and deep coverage on the subject explained

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