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VLSI Verification

VLSI Verification

  • 5.0 | 16 Ratings
  • 142 Students enrolled
  • Certified course

About Course

  Language English

VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail.

As part of SystemVerilog for Verification module it trains you extensively on creating the testbenches using OOP, constraint random simulation and verification sign-off using functional coverage. Finally, it also walks you through UVM methodology concepts and explains the need of using IEEE standard methodologies like UVM to create SystemVerilog based testbenches.

USP : This course is very different from the standard textbooks and training courses available in the market. This verification course is completely based on a standard testbench architecture which can be used for creating SystemVerilog testbenches and at the same they can be easily migrated to UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.

Any electronics engineer with a good knowledge in RTL design using Verilog HDL can learn all the verification methodologies and SystemVerilog language concepts from this course and grow as a hand-on verification expert.

Modules:

  • Verification Methodology Overview
  • Systemverilog for Verification
  • Universal Verification Methodology Overview

Prerequisite: Any electronics/electrical engineering graduate with a good knowledge in RTL design using Verilog HDL.

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Curriculum

  • 1: Verification Methodology Overview

  • Lecture 1 Introduction to Verification Methodology 22:24
  • Lecture 2 Verification Process 21:46
  • Lecture 3 Reusable TB 07:24
  • Lecture 4 Verification Environment Architecture 19:01
  • Lecture 5 Constraint Random Coverage Driven Verification 25:36
  • Lecture 6 Verification Methodologies & Summary 27:11
  • Quiz 1 Knowledge Check - Verification Methodology Overview 15 Questions
  • 2: SystemVerilog Language Concepts

  • Lecture 7 SV Concepts Agenda 06:37
  • Lecture 8 SV Overview 11:15
  • Lecture 9 SV Transactions 14:46
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Reviews

5.0
16 Ratings
5 100% 4 0% 3 0% 2 0% 1 0%
  • Kevin Mathew
    12 January 2020

    Every concept has been explained in detail with examples. Also the practical examples like SOC TB architecture helped me to understand how we can apply the SV concepts.

  • Rajeshwari
    11 January 2020

    Experienced verification expert explaining the concepts practically is a great thing about this course. Learning becomes very easy because of his explanations.

  • Mark
    9 January 2020

    I like the way the trainer explains the concepts in detail. I was able to watch the videos repeatedly and discuss my doubts during live Q&A. It helped me so much to understand the concepts clearly. I would say this is much better than the class room session.

  • Rebecca
    6 January 2020

    Practical examples like SOC verification flow were very useful to understand why we need SystemVerilog to verify the complex chips. This is one of the best online courses that I would highly recommend to the engineers who want to become verification experts.

  • Rakshith
    5 January 2020

    Very good explanation, The way he explains the concepts makes me feel that he is sitting along with me and explaining the concepts nicely. I am enjoying the course.

  • Meha
    1 January 2020

    Excellent course to study online. The explanation is Awesome and very practical.

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