VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail.
As part of SystemVerilog for Verification module it trains you extensively on creating the testbenches using OOP, constraint random simulation and verification sign-off using functional coverage. Finally, it also walks you through UVM methodology concepts and explains the need of using IEEE standard methodologies like UVM to create SystemVerilog based testbenches.
USP : This course is very different from the standard textbooks and training courses available in the market. This verification course is completely based on a standard testbench architecture which can be used for creating SystemVerilog testbenches and at the same they can be easily migrated to UVM framework. Also, we use two main examples throughout the course to explain all the methodology and language concepts. One is a small dual port RAM RTL design which is used for explaining all the language concepts in detail, especially for the testbench implementation. The other one is a complex SOC design which is used for explaining the use-cases of certain SystemVerilog language features and challenges of migrating IP level testbenches to SOC level testbenches.
Any electronics engineer with a good knowledge in RTL design using Verilog HDL can learn all the verification methodologies and SystemVerilog language concepts from this course and grow as a hand-on verification expert.
Prerequisite: Any electronics/electrical engineering graduate with a good knowledge in RTL design using Verilog HDL.Read full details
2: Verification Methodology Overview
3: SystemVerilog Reference Book - Download FYR
4: SystemVerilog Language Concepts
amazing course helps you get an in-depth idea of the basic concepts
it's really good
I found it very helpful
This course laid good fundamentals on the VLSI Verification Process using System Verilog basically followed by introduction to UVM at the end of the course. The hands on labs and course projects were really helpful for having a better learning process.
Wonderful course to learn verification! Loved the way Mr. Shiv kumar explained the concepts with great examples, especially Object oriented programming.
the course was really helpful to understand the concepts indepth
Course was good
Very useful for beginners
Best course to learn SysVerilog
It is an ultimate course covered all the concept in well demonstrated manner. I felt happy and happy enjoyed alot during course and will be always wanted myself to learn the concepts
it was a nice learning
The content is really very in detail and the explanation of each topic is quite satisfactory. The course structure is also great.
Concepts are well explained
It was really helpful to understand the way in which verification is done and is well explained
Very good course for concepts of Constraint Driven Verification using System Verilog
It's an wonderful experience and really good course for beginners to start from scratch and become expertise... thank you Sivakumar sir for this amazing course.
I just finished the course and still following the steps as instructed by Sivakumar sir... So far it is very easy to learn as a beginner.. Thanks for the great course!
excellent...the course is so helpful
Covers the basics of sv well..
Very well laid out course, seems perfect for a beginner like me.
Concepts are explained in a lucid and elaborate manner hence it is a must for beginners in vlsi verification.
The course is the best place to learn system verilog - as it's a niche subject and information is not readily available everywhere. So if you want to skip the hassle of reading multiple books, this course is what you're looking for.
very well organized and disciplined topic covered
An excellent course; I highly recommend it.
This is a very good course.
Fantastic course for beginners.
Good theory in course
Great course for those who are new in VLSI-verification field. All the concepts of verification i.e Frontend Verification and Backend Verification are precisely explained. Also concepts of System Verilog are explained in very great manner. One of the Add-Ons i observed in the course is that case study is been included which really clears your concept in depth. Thank you very much Sivakumar Sir for designing such a great course.
Everything explained in very precised manner.
Elaboration of concepts are very clear
Looks good. This might help to get overview of SV module
The course is perfect for learning nuances!
well explanation every concept with examples.
This course is excellent. I like the way how he taught the concepts.
this course is very useful
Course is clear and easily understandable
My VLSI Verification and System Verilog course experience in Maven Silicon has been great. Video explanations are very clear. Trainers explain each and every topic in a precise way. The Q&A sessions are up to the mark, the technical support members are very active and they cleared my doubts in no time. I will consider my experience with this organization as a big step in the future. Thank you for this wonderful teaching.
The staffs are always ready to clarify the doubts of ours at any time. If you are really interested in VLSI domain ,MAVEN SILICON will help you to gain more knowledges .It has an Excellent content which helps to improve ourselves in this domain field.
The journey with the Maven Silicon is incredible the way of teaching and course content is good. The course content mainly cover related to industry level u will get to know how the industry is going on and they will teach from the scratch itself so that we can easily understand the concepts . And technical staffs are really good whatever we have doubts we can clarify in the Live Q&A sessions which will be held in the weekends or in the WhatsApp group the staff are very interactive and very supportive they will clarify the doubts within 24hrs. The journey with the Maven Silicon is really great .
I think this course is one of the best courses that I have ever come across. The support team is really great. The explanation in the videos is really good. And Satish sir is such a great mentor and support throughout the course. The whole team supported during any queries that I have faced during the course. And I am really thankful to the whole Maven family for this.
Every concept has been explained in detail with examples. Also the practical examples like SOC TB architecture helped me to understand how we can apply the SV concepts.
Experienced verification expert explaining the concepts practically is a great thing about this course. Learning becomes very easy because of his explanations.
I like the way the trainer explains the concepts in detail. I was able to watch the videos repeatedly and discuss my doubts during live Q&A. It helped me so much to understand the concepts clearly. I would say this is much better than the class room session.
Practical examples like SOC verification flow were very useful to understand why we need SystemVerilog to verify the complex chips. This is one of the best online courses that I would highly recommend to the engineers who want to become verification experts.
Very good explanation, The way he explains the concepts makes me feel that he is sitting along with me and explaining the concepts nicely. I am enjoying the course.
Excellent course to study online. The explanation is Awesome and very practical.